1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for selectively performing fetches for store operations during speculative execution. relates to a method and an apparatus for selectively performing fetches for store operations during speculative execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two cache or main memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed using speculative-execution modes to avoid the pipeline stalls associated with cache line misses. Two of these speculative-execution modes are: (1) execute-ahead mode and (2) scout mode.
Execute-ahead mode operates as follows. During normal execution, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.
If the unresolved data dependency is resolved during execute-ahead mode, the system enters a deferred execution mode, wherein the system executes deferred instructions. If all deferred instructions are executed during this deferred execution mode, the system returns to normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.
If the system encounters a non-data-dependent stall condition while executing in normal mode or execute-ahead mode, the system moves to a scout mode. In scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. When the launch point stall condition (the unresolved data dependency or the non-data dependent stall condition that originally caused the system to move out of normal execution mode) is finally resolved, the system uses the checkpoint to resume execution in normal mode from the launch point instruction (the instruction that originally encountered the launch point stall condition).
By allowing a processor to continue to perform work during stall conditions, speculative-execution can significantly increase the amount of work the processor completes.
However, certain operations, such as stores, can become complicated during speculative-execution. During normal execution, a store instruction takes place as follows. First the system generates a fetch for a cache line associated with the store. Next, the system places the store into a store buffer and waits for the cache line to be fetched into the cache. When the fetch eventually returns the cache line, the store from the store buffer is written to the cache line.
Note that a fetch may not be necessary because the cache line already has a store pending in the store buffer which has generated a fetch for the cache line or the cache line is already present in the L1 data cache. In these cases, valuable memory system bandwidth can be saved if the fetch is not generated.
During speculative execution, as in normal execution, fetches are generated for store instructions. However, these fetches may be unnecessary because the cache line is currently being fetched or is already present in the L1 data cache.
Hence, what is needed is a processor which selectively fetches cache lines for store operations.